/*
 *  DaVinci Power & Sleep Controller (PSC) defines
 *
 *  Copyright (C) 2006 Texas Instruments.
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 *
 */
#ifndef __PSC_H__
#define __PSC_H__

#include "hardware.h"

/* Power and Sleep Controller (PSC) Domains */
#define DAVINCI_GPSC_ARMDOMAIN      0
#define DAVINCI_GPSC_DSPDOMAIN      1

#if defined(CONFIG_SOC_DM646X) //reference to spruep9e - DM646x ARM subsystem page 62
#define LPSC_ARM            0
#define LPSC_DSP_C64X       1
#define LPSC_HDVICP0        2
#define LPSC_HDVICP1        3
#define LPSC_EDMA3CC        4
#define LPSC_EDMA3TC0       5
#define LPSC_EDMA3TC1       6
#define LPSC_EDMA3TC2       7
#define LPSC_EDMA3TC3       8   
#define LPSC_USB            9
#define LPSC_ATA            10
#define LPSC_VLYNQ          11
#define LPSC_HPI            12
#define LPSC_PCI            13
#define LPSC_EMAC           14
#define LPSC_VDCE           15
#define LPSC_VPSSMSTR       16
#define LPSC_VPSSSLV        17
#define LPSC_TSIF0          18
#define LPSC_TSIF1          19
#define LPSC_DDR_EMIF       20
#define LPSC_AEMIF          21
#define LPSC_McASP0         22
#define LPSC_McASP1         23
#define LPSC_CRGEN0         24
#define LPSC_CRGEN1         25
#define LPSC_UART0          26
#define LPSC_UART1          27
#define LPSC_UART2          28
#define LPSC_PWM0           29
#define LPSC_PWM1           30
#define LPSC_I2C            31
#define LPSC_SPI            32
#define LPSC_GPIO           33
#define LPSC_TIMER0         34
#define LPSC_TIMER1         35
//RESERVED
#define LPSC_ARM_INTC       45
#elif defined(CONFIG_SOC_DM36X) //reference to sprufg5a - DM36x ARM subsystem page 71
#define LPSC_EDMACC         0
#define LPSC_EDMATC0        1
#define LPSC_EDMATC1        2
#define LPSC_EDMATC2        3
#define LPSC_EDMATC3        4
#define LPSC_TIMER3         5
#define LPSC_SPI1           6
#define LPSC_MMC_SD1        7
#define LPSC_McBSP          8
#define LPSC_USB            9
#define LPSC_PWM3           10
#define LPSC_SPI2           11
#define LPSC_RTO            12
#define LPSC_DDR2_EMIF      13
#define LPSC_AEMIF          14
#define LPSC_MMC_SD0        15
//RESERVED
#define LPSC_TIMER4         17
#define LPSC_I2C            18
#define LPSC_UART0          19
#define LPSC_UART1          20
#define LPSC_HPI            21
#define LPSC_SPI0           22
#define LPSC_PWM0           23
#define LPSC_PWM1           24
#define LPSC_PWM2           25
#define LPSC_GPIO           26
#define LPSC_TIMER0         27
#define LPSC_TIMER1         28
#define LPSC_TIMER2         29
#define LPSC_SYSTEM         30
#define LPSC_ARM            31
//RESERVED
#define LPSC_EMULATION      35
//RESERVED
#define LPSC_SPI3           38
#define LPSC_SPI4           39
#define LPSC_EMAC           40
#define LPSC_PRTCIF         41
#define LPSC_KEYSCAN        42
#define LPSC_ADC            43
#define LPSC_VOICE_CODEC    44
#define LPSC_VDAC_CLKREC    45
#define LPSC_VDAC_CLK       46
#define LPSC_VPSSMASTER     47
//RESERVED
#define LPSC_MJCP           50
#define LPSC_HDVICP         51
#elif defined(CONFIG_SOC_DM644X)

#elif defined(CONFIG_SOC_DA8XX)

#endif

//PSC Registers
#if defined(CONFIG_SOC_DM646X)
#define PSC_PID                (DAVINCI_PWR_SLEEP_CNTRL_BASE + 0x0) //Peripheral Revision and Class Information Register
#define PSC_INTEVAL            (DAVINCI_PWR_SLEEP_CNTRL_BASE + 0x18) //Interrupt Evaluation Register
#define PSC_MERRPR0            (DAVINCI_PWR_SLEEP_CNTRL_BASE + 0x40) //Module Error Pending 0(mod 0-31) Register
#define PSC_MERRPR1            (DAVINCI_PWR_SLEEP_CNTRL_BASE + 0x44) //Module Error Pending 1(mod 32-63) Register
#define PSC_MERRCR0            (DAVINCI_PWR_SLEEP_CNTRL_BASE + 0x50) //Module Error Clear 0 (mod0-31) Register
#define PSC_MERRCR1            (DAVINCI_PWR_SLEEP_CNTRL_BASE + 0x54) //Module Error Clear 1 (mod32-63) Register
#define PSC_PTCMD              (DAVINCI_PWR_SLEEP_CNTRL_BASE + 0x120) //Power Domain Transition Command Register
#define PSC_PTSTAT             (DAVINCI_PWR_SLEEP_CNTRL_BASE + 0x128) //Power Domain Transition Status Register
#define PSC_MDSTAT_BASE		   (DAVINCI_PWR_SLEEP_CNTRL_BASE + 0x800) 
#define PSC_MDCTL_BASE		   (DAVINCI_PWR_SLEEP_CNTRL_BASE + 0xA00) 
#elif defined(CONFIG_SOC_DM36X)
#define PSC_PID                (DAVINCI_PWR_SLEEP_CNTRL_BASE + 0x0) //Peripheral Revision and Class Information Register
#define PSC_INTEVAL            (DAVINCI_PWR_SLEEP_CNTRL_BASE + 0x18) //Interrupt Evaluation Register
#define PSC_MERRPR0            (DAVINCI_PWR_SLEEP_CNTRL_BASE + 0x40) //Module Error Pending 0(mod 0-31) Register
#define PSC_MERRPR1            (DAVINCI_PWR_SLEEP_CNTRL_BASE + 0x44) //Module Error Pending 1(mod 32-63) Register
#define PSC_MERRCR0            (DAVINCI_PWR_SLEEP_CNTRL_BASE + 0x50) //Module Error Clear 0 (mod0-31) Register
#define PSC_MERRCR1            (DAVINCI_PWR_SLEEP_CNTRL_BASE + 0x54) //Module Error Clear 1 (mod32-63) Register
#define PSC_PTCMD              (DAVINCI_PWR_SLEEP_CNTRL_BASE + 0x120) //Power Domain Transition Command Register
#define PSC_PTSTAT             (DAVINCI_PWR_SLEEP_CNTRL_BASE + 0x128) //Power Domain Transition Status Register
#define PSC_MDSTAT_BASE		   (DAVINCI_PWR_SLEEP_CNTRL_BASE + 0x800) 
#define PSC_MDCTL_BASE		   (DAVINCI_PWR_SLEEP_CNTRL_BASE + 0xA00) 
#endif

/* PSC module states */
#define PSC_STATE_SWRSTDISABLE	0
#define PSC_STATE_SYNCRST	1
#define PSC_STATE_DISABLE	2
#define PSC_STATE_ENABLE	3

#define MDSTAT_STATE_MASK 0x1f

#endif
